The present disclosure relates to technology for non-volatile memory.
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM. The array of storage elements may be divided into a large number of blocks of storage elements.
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (Vth) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate. Thus, a storage element may be read by applying a reference voltage to its control gate and sensing the magnitude of the current that flows between its drain and source.
A storage element may be programmed by applying suitable programming voltages to its control gate. Typically, a program voltage Vpgm applied to the control gate during a program operation is applied as a series of pulses that increase in magnitude over time.
Typically, the Vth of the memory cell varies with temperature. If the same memory cell is read at different temperatures, its Vth typically shifts lower as the temperature increases. The Vth shift per temperature unit is defined as the Temperature Coefficient (or simply Tco) for that memory cell. For some devices, Tco is a negative quantity since the Vth reduces as the temperature increases.
This shift is depicted in FIG. 1, which shows two sets of threshold voltage distributions. One set is for a high temperature read, the other for a low temperature read. However, each set was programmed at the same temperature. Each set has a threshold voltage distribution for an A-state, B-state, and C-state. A portion of the erase-state is also shown. The threshold voltage distribution for a given state shows the range of Vths for memory cells programmed to that state. Example read levels (VrA, VrB, VrC) are shown for the low temperature distributions. Example read levels (VrA′, VrB′, VrC′) are shown for the high temperature distributions. For accurate reading, the read levels may be about midway between two adjacent threshold voltage distributions. Note that the y-axis is a log scale of the number of memory cells.
One possible way to compensate for this Vth temperature dependence is to determine read levels according to an equation such as Equation 1.R(atT)=R0+Tco*T  Eq. 1
In Equation 1, R is the read level for a given state, R0 is a base read reference voltage for that state, T is the temperature during read, and Tco is the temperature coefficient which may be optimized by matching it with the memory cell Tco. Note that Tco may be a function of the state being read. As one example, a result of applying Equation 1 may be to determine level VrB for the low-temperature read and VrB′ for the high-temperature read (see FIG. 1). Thus, a compensation that is based on the dependence of the memory cell's Vth on temperature may be applied to the read levels.
Further complicating the situation is that the memory cells could be programmed at different temperatures. For example, memory cells in one block (or some other unit) in the memory could be programmed at a high temperature and another block at a low temperature. In one scenario, the different blocks may be read back at the same read temperature. For example, there may be a high-temperature program paired with a high-temperature read, as well as a low-temperature program paired with a high-temperature read. In another scenario, the different blocks may read back at different read temperatures. For example, there may be a high-temperature program paired with a high-temperature read, as well as a low-temperature program paired with a low-temperature read.
If the same program verify levels are used at different temperatures, it would lead to different Vth distribution positions for the blocks programmed at different temperatures due to the Tco of the memory cells. This is true even if both blocks are read at the same temperature. This is also true even if temperature compensation is used during read for the case that reading is performed at different temperatures. Thus, simply having a Tco on read levels is not sufficient to take care of different programming temperatures.
To resolve the problem of different programming temperatures, the same Tco may also be applied to all the verify levels (not depicted in FIG. 1). As one example, the verify levels will also follow Equation 1 (but with verify levels instead of read levels). At lower temperatures, the verify levels for all states will be higher than what they would be at higher temperature. Thus, if both blocks are read back with optimized voltage Tco, the Vth distributions would align at the same position no matter the temperature the programming was done at.
Note that to achieve the above, the value for Tco used on read/verify levels needs to be optimized such that it matches with the memory cell Tco (the rate at which typical cell's Vth moves with temperature). Also there may be state dependency in the memory cell Tco, which means different Tco values may be used to determine read and verify reference levels for different states.